1. Field of the Invention
The present invention relates generally to the field of semiconductor device fabrication and more particularly to the field of contact processing in semiconductor device fabrication.
2. Description of the Related Art
Prior art contact processes for semiconductor devices, e.g., erasable programmable read-only memories (EPROM's) or other non-volatile semiconductor memory devices, have required a contact-to-gate spacing of 0.3-0.5 .mu.m to avoid accidental shorts between the gate and the contact filling connecting the diffusion region. FIG. 1, for example, shows a partial top view of a semiconductor memory device where a significant space between two elongated, parallel polycrystalline silicon (polysilicon) word lines 130 is required to allow the placement of contact filling 120 using conventional contact processes without causing a short between the diffusion contact 120 and either word line 130.
FIG. 2 is a partial cross-sectional view of FIG. 1 and more clearly depicts the contact-to-gate spacing required for prior art contact processes. In FIG. 2 each gate stack 135 formed on semiconductor substrate 110 includes a gate oxide layer 131, a first polysilicon layer 132 which serves as a floating gate, an insulative or dielectric layer 133, a second polysilicon layer 130 which serves as a word line or control gate, and an outer insulative oxide layer 134. The semiconductor substrate 110 includes appropriate diffusion regions, such as source regions 111 and 113 and drain region 112, as is well known in the art. The semiconductor substrate 110 and both stacks 135 are disposed in an upper oxide layer 121 where an opening is formed between the two stacks 135 and filled with a metal to form contact filling 120, thus providing an available connection to diffusion or drain region 112. Because stacks 135 are sufficiently spaced apart from one another in FIG. 2, the contact opening and filling 120 are safely formed without causing any diffusion contact to gate shorts.
Without a sufficient contact-to-gate spacing allocation, though, portions of the oxide layer 134 encapsulating each gate stack 135 could potentially get etched away during the contact opening etch in upper oxide layer 121. This could happen, for example, if the patterning layer created for the contact opening etch was not accurately aligned for the etch between gate stacks 135 and/or if the contact opening etched in the upper oxide layer 121 was too large for any given gate-to-gate spacing. As a result, word line 130 and/or floating gate 132 of either or both gate stacks 135 would then become exposed to contact filling 120, rendering the exposed stack(s) inoperable because of the now created diffusion contact to gate short. Contact lithography in the prior art is thus constrained by alignment and contact size requirements for any given gate-to-gate spacing.
While the gate-to-gate spacing could always be made large enough to safely avoid diffusion contact to gate shorts and make contact lithography easier (i.e., with less stringent alignment and contact size requirements), this consideration must be weighed against the high desirability of fabricating semiconductor devices with smaller cell sizes and increased cell densities. Minimizing the contact opening size has been considered not only to avoid diffusion contact to gate shorts but also to help minimize the cell size of the semiconductor device, and hence increase cell density. However, a sufficient contact-to-gate spacing is still required to allow for any misalignment of the patterning layer in etching the contact opening. Furthermore, minimizing the size of contact openings makes contact lithography more difficult and is usually limited by the resolution and depth of focus capability of the patterning technology used.
What is thus needed is a semiconductor device fabrication process which is less sensitive to any misalignment in the patterning layer created for the contact opening etch to reduce or eliminate the contact-to-gate spacing requirement. What is also needed is a semiconductor device fabrication process which is less sensitive to contact size to allow for larger contact openings to be etched in the photoresist layer regardless of the desired cell size for a given semiconductor device, thus making contact lithography processing easier.